VERILOG       := top.v \
								 attosoc.v \
								 simpleuart.v \
								 pll.v \
								 kianv_harris_mc_edition.v \
								 control_unit.v  \
								 datapath_unit.v \
								 register_file.v \
								 design_elements.v \
								 alu.v \
								 main_fsm.v \
								 extend.v \
								 alu_decoder.v \
								 store_alignment.v \
								 store_decoder.v \
								 load_decoder.v \
								 load_alignment.v \
								 multiplier_extension_decoder.v \
								 divider.v \
								 multiplier.v \
								 divider_decoder.v \
								 multiplier_decoder.v \
								 csr_unit.v \
								 csr_decoder.v
DEVICE = 85k
#DEVICE = 25k

include ./ulx3s.mk


